bufg bufh bufgce bufhce


How to use two gtx transceivers in one quad for two aurora ips

hera mgt bank is 113 i am using two aurora ips 64b66b .for one ip GTX_X1Y0, another GTX_X1Y2.while simulating ,results are good.Coming to implementation its showing error in implementaion.that in MAP. Pack:2811 - Directed packing was unable to obey t... Read More

Vivado 2014.2 MMCM and BUFGMUX multiple syncronous clock

Hi, I am working on KC705 and I use Vivado 2014.2. The block diagram of the clocking structure and the system as below. I generated 3 clocks (250 MHz, 125 MHz, 62.5 MHz) from the input clock (250 MHz).  Because of the BUFG-BUFG error I select clockin... Read More

Difference between center,edge mmcm and edge direct allignments

What is the difference between center, edge mmcm and edge direct allignments.Both of these terms are used most often used (but not exclusively) when describing source synchronous interfaces. Edge Aligned vs. Center Aligned When a device uses source s... Read More

How to remove the bufgs that are not being used

Hi, I have a IP block that has BUFGs that may or may not be used depending on which design the IP block is used. If they are not used I would like them to be removed but the tools are not consistent, sometimes they remove them and sometimes they do n... Read More

Bufg in entities from tables wizard

Environment Win XP 5.1.2600 Spanish; Jdeveloper 10132 with this table SQL> desc linea; Name                                      Null?    Type CODPROV                             NOT NULL VARCHAR2(3) CODLINE                               NOT NULL VAR... Read More

Multiple clock domains each with clock mulitplexing. Solve warning (Place 30-568])

My design can be partitioned in several clock regions (up to 20 for now). In each region I've instantiated a PLL and each PLL generates 4 clocks. I need to multiplex these 4 clocks per each region and to clock gate the output based on a signal in the... Read More

PAR done but shows PAR Error on planahead 14.7

hi, am getting PAR error while in log it shows PAR done!!! this happens only when i change the reset pin of my design from V5 to any other pin. my design consists of microblaze also. Thanksfollowing is the logi file *** Running ngdbuild with args -in... Read More

Philadelphia Area Hold Time

I called AT&T at 11:00 am and held for over 40 minutes then was disconnected. I have now been on hold for 38:40 and am still on hold. I don't care what the problem is, this is ridiculous. Faith(You know what the answer is going to be...) Don't do tha... Read More

Can't simulate Clocking Wizard in ISE 14.7

Hi! I have developed a simple design for a VGA module where I need to produce a 40Mhz clock out of 100Mhz input for an Artix-7 (XC7A100T-CSG324) on an Digilent Nexys4 evaluation board. In order to aquire this clock I have used a Clock Wizard for a DC... Read More

How to use a pll output to drive the clock input?

when i use the following code to generate a clock(CLK00IN) from MHZIN to drive the normal logic,it work normally,but when i use it to drive the gtp clock  input  port CLK00,CLK00IN become 0 (no signal),why? IBUFG system_clk_ibufg  .O                 ... Read More

IDELAYCTRL REFCLK pin should be connected.

I have a Virtex-7 design that uses IDELAYE2 and ODELAYE2 primitives. I have instantiated a single IDELAYCTRL primitive in my code which is supposed to service all IDELAYE2 and ODELAYE2 primitives in my design. IDELAYCTRL receives 200 MHz clock genera... Read More

Par failing on EDK 11.4

Dear forum members, I've designed a system on custom board using the spartan-6 lx45t device on EDK 11.4 using the base system builder. Following is the device utilization summary after map:     Number of LOCed IOBs                  97 out of 97    10... Read More

Problems diplaying image on double buffered Panel

Hello, I made a very simple image visualizer using double buffer. I load the images using ImageIO.read(File file) and display the image on the Panel by drawing it first to a buffer Image using a buffer Graphics, and then painting the buffer Image on... Read More

Source Synchronous Input: Capture clock/Launch Clock analysis

Hi, I have a Source Synchronous LVDS DDR input into a Kintex7, the launching clock is edge-aligned to the data and capture clock should capture on opposite edge (a launch on the rising edge should be captured by the falling edge). I have designed it... Read More

Painting components to buffers

Hi, My class, GamePanel, is extending JPanel and implementing Runnable, therefore all my painting is done in run(). I am using a buffer to draw images on, I would also like to draw Component�s on it as well. Here is the code I�m using to draw the Com... Read More

Spartan 6 LX100 - synthesys OK but Place:543 error when mapping

Hi all, I am currently working on a code for a Spartan 6 LX100 and I have about 70% of the code ready. I have decided to implement the design half-way to avoid any surprises at the end and well, it didn't fit. When I synthesyze the design it appears... Read More

Issues with placing IBUGDS, Vivado 2014.2

Hi all, I am currently using this device xc7z045ffg676-1 and am having issues with making a HR port  LVDS_25  input pair at pins AE25 and AE26 a clock source.   The verilog code for the instantation of  the port as a clock input is as followes module... Read More

XST producing seemingly random results

Hi, I have a circuit which I am synthesizing in XST and eventually building into a bit file. The problem is that some times the bitfile doesn't work and simply regenerating the netlist with a change in some parameter (say Safe Implementation) and no... Read More


Hi Guys how about some help! I am new to DDR3 WHAT IS THE FASTEST MEMORY I CAN RUN IN MY NEW MAINBOARD 790FX-GD70. 955 AMD PHENOM. Lat on DDR3 memory is all over the place lat6,lat7,lat8.What is the best timing to run Some people lat8-8-8-18. I would... Read More

MIG DDR3 on Virtex-6 - Unroutable situation in PaR

Hello, I have a SP6 design with MIG and at P&R I get this warning: WARNING:Route:436 - The router has detected an unroutable situation for one or more connections. The router will finish the rest of the design and leave them as unrouted. The cause of... Read More